1. Field of the Invention
The present invention relates to an error recovery system and method in a data processor for pipeline processing, more particularly to a system and method for recovering from an error of control storage in a data processor which is controlled by microinstructions stored in the control storage and which carries out pipeline processing.
2. Description of the Related Art
In known data processors which carry out pipeline processing of machine instructions, an error in the microinstructions read from the control storage which stores the microinstructions can obstruct the correct execution of the entire pipeline. Accordingly, in pipeline processing, an error correction code is provided in the microinstructions stored in the control storage, and the detection and correction of the error in the read-out microinstructions are carried out.
More specifically, microinstructions relating to the pipeline processing are stored in the control storage. When a microinstruction is read out, it is written in a data register. A decoder decodes the instruction in the data register to transmit it to each control point, which carries out the pipeline processing, and to the instruction is sent to the microinstruction register for a succeeding cycles.
On the other hand, the contents of the microinstructions are read out into an error detection and correction circuit. Then, an error correction code is employed to check whether there is an error bit in the instruction. When no error is detected, a pipeline controller carries out a predetermined operation according to the instruction. The pipeline controller 15 generates an instruction release signal during each cycle of the pipeline processing to execute each cycle of D(decode), A(address generation), T(translation), B(buffer access), E(execution), and W(write) normally which allows the microinstruction to be applied to the corresponding pipeline stages. The decoding of read-out machine instructions is carried out in the D cycle, an address calculation for an operand is carried out in the A cycle, an address translation of the address is carried out in the T cycle, a buffer or register is accessed in the B cycle, execution processing is carried out on the data read-out from the buffer or register in the E cycle, and the write operation for processed results is carried out in the W cycle.
When an error is detected in the instruction read out by the data register, the operation of the pipeline controller is halted and an interlock is carried out in the pipeline. In the course of interlocking, the error in the instruction is corrected in the data register and a rewrite of the correct instruction into the control storage is carried out. The error correction code can generally detect and correct a 1-bit error. For a 2-bit error, use is made of a single-error correction double-error-detection (SEC. DED) code, which can only detect 2-bit errros.
It would take considerable time for this prior art error detection and correction circuit not only to correct errors, but even to detect errors. Because of this, it has been necessary to provide an exclusive correction cycle to detect and correct errors every time an instruction is read out. The addition of such a correction cycle to the normal pipeline processing cycles, however, results in excessive augmentation of the entire pipeline processing time, so is not preferable with respect to performance. Further, when an error is detected in an instruction read out of the control storage, the processing of the machine instruction is stopped and then reexecuted in machine instruction units. In the case of a machine instruction which realizes its function through a plurality of flows, however, in some cases, the write operation to the register is performed in a flow prior to the faulty flow, and it is impossible to return to the original state before the instruction was run for reexecution (this is called "over retriable point"). In such a case, the error cannot be corrected.